circuit group :
  extmodule BUFG :
    input I : Clock
    output O : Clock
    defname = BUFG

  module transfer :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, cardio : { flip card_group_data : UInt<2>, flip card_group_cmd : UInt<1>, group_card_state : UInt<1>, group_card_result : UInt<8>}, flip emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[transfer.scala 31:19]
    reg io_emitterio_fpga_cim_data_r : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_emitterio_fpga_cim_data_r <= io.cardio.card_group_data @[Reg.scala 29:22]
    io.emitterio.fpga_cim_data <= io_emitterio_fpga_cim_data_r @[transfer.scala 33:32]
    reg io_emitterio_fpga_cim_cmd_r : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_emitterio_fpga_cim_cmd_r <= io.cardio.card_group_cmd @[Reg.scala 29:22]
    io.emitterio.fpga_cim_cmd <= io_emitterio_fpga_cim_cmd_r @[transfer.scala 34:32]
    reg io_cardio_group_card_result_r : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_cardio_group_card_result_r <= io.emitterio.cim_fpga_result @[Reg.scala 29:22]
    io.cardio.group_card_result <= io_cardio_group_card_result_r @[transfer.scala 35:34]
    reg io_cardio_group_card_state_r : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_cardio_group_card_state_r <= io.emitterio.cim_fpga_state @[Reg.scala 29:22]
    io.cardio.group_card_state <= io_cardio_group_card_state_r @[transfer.scala 36:34]

  extmodule BUFG_1 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_1 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_2 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_1 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_2 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_3 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_2 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_3 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_4 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_3 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_4 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_5 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_4 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_5 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_6 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_5 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_6 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_7 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_6 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_7 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_8 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_7 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_8 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_9 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_8 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_9 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_10 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_9 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_10 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_11 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_10 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_11 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_12 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_11 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_12 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_13 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_12 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_13 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_14 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_13 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_14 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_15 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_14 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_15 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  extmodule BUFG_16 :
    input I : Clock
    output O : Clock
    defname = BUFG

  module emitter_15 :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, flip enable : UInt<1>, emitterio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}}

    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[emitter.scala 34:19]
    reg data : UInt, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      data <= io.emitterio.fpga_cim_data @[Reg.scala 29:22]
    reg cmd : UInt<1>, io.systemclk with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      cmd <= io.emitterio.fpga_cim_cmd @[Reg.scala 29:22]
    io.chipio.fpga_cim_data <= data @[emitter.scala 38:33]
    io.chipio.fpga_cim_cmd <= cmd @[emitter.scala 39:33]
    inst BUFG of BUFG_16 @[emitter.scala 41:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.chipio.cim_fpga_clk @[emitter.scala 42:12]
    reg state : UInt<1>, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      state <= io.chipio.cim_fpga_state @[Reg.scala 29:22]
    reg result : UInt, BUFG.O with :
      reset => (systemRst, UInt<1>("h0")) @[Reg.scala 28:20]
    when io.enable : @[Reg.scala 29:18]
      result <= io.chipio.cim_fpga_result @[Reg.scala 29:22]
    io.emitterio.cim_fpga_state <= state @[emitter.scala 46:35]
    io.emitterio.cim_fpga_result <= result @[emitter.scala 47:35]

  module group :
    output io : { flip systemclk : Clock, flip systemRstn : UInt<1>, cardio : { flip card_group_data : UInt<2>, flip card_group_cmd : UInt<1>, group_card_state : UInt<1>, group_card_result : UInt<8>}, flip chipio : { flip fpga_cim_data : UInt<2>, flip fpga_cim_cmd : UInt<1>, cim_fpga_state : UInt<1>, cim_fpga_clk : Clock, cim_fpga_result : UInt<8>}[16], dcout : { cim_dcdata : UInt<4>, cim_dcvld : UInt<1>}, flip dcin : { cim_dcdata : UInt<4>, cim_dcvld : UInt<1>}}

    inst BUFG of BUFG @[group.scala 15:22]
    BUFG.O is invalid
    BUFG.I is invalid
    BUFG.I <= io.systemclk @[group.scala 16:12]
    node systemRst = eq(io.systemRstn, UInt<1>("h0")) @[group.scala 17:19]
    reg io_dcout_cim_dcdata_REG : UInt, BUFG.O with :
      reset => (UInt<1>("h0"), io_dcout_cim_dcdata_REG) @[group.scala 20:35]
    io_dcout_cim_dcdata_REG <= io.dcin.cim_dcdata @[group.scala 20:35]
    io.dcout.cim_dcdata <= io_dcout_cim_dcdata_REG @[group.scala 20:25]
    reg io_dcout_cim_dcvld_REG : UInt<1>, BUFG.O with :
      reset => (UInt<1>("h0"), io_dcout_cim_dcvld_REG) @[group.scala 21:35]
    io_dcout_cim_dcvld_REG <= io.dcin.cim_dcvld @[group.scala 21:35]
    io.dcout.cim_dcvld <= io_dcout_cim_dcvld_REG @[group.scala 21:25]
    reg counter : UInt<5>, BUFG.O with :
      reset => (systemRst, UInt<5>("h0")) @[group.scala 23:26]
    node _counter_T = lt(counter, UInt<5>("h10")) @[group.scala 24:28]
    node _counter_T_1 = add(counter, UInt<1>("h1")) @[group.scala 24:50]
    node _counter_T_2 = tail(_counter_T_1, 1) @[group.scala 24:50]
    node _counter_T_3 = mux(_counter_T, _counter_T_2, UInt<1>("h0")) @[group.scala 24:19]
    counter <= _counter_T_3 @[group.scala 24:13]
    wire enable_array : UInt<1>[16] @[group.scala 25:31]
    enable_array[0] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[1] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[2] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[3] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[4] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[5] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[6] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[7] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[8] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[9] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[10] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[11] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[12] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[13] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[14] <= UInt<1>("h0") @[group.scala 25:31]
    enable_array[15] <= UInt<1>("h0") @[group.scala 25:31]
    inst transfer of transfer @[group.scala 27:26]
    transfer.io.systemclk <= io.systemclk @[group.scala 28:24]
    transfer.io.systemRstn <= io.systemRstn @[group.scala 29:25]
    io.cardio.group_card_result <= transfer.io.cardio.group_card_result @[group.scala 30:21]
    io.cardio.group_card_state <= transfer.io.cardio.group_card_state @[group.scala 30:21]
    transfer.io.cardio.card_group_cmd <= io.cardio.card_group_cmd @[group.scala 30:21]
    transfer.io.cardio.card_group_data <= io.cardio.card_group_data @[group.scala 30:21]
    inst emitter of emitter @[group.scala 32:46]
    inst emitter_1 of emitter_1 @[group.scala 32:46]
    inst emitter_2 of emitter_2 @[group.scala 32:46]
    inst emitter_3 of emitter_3 @[group.scala 32:46]
    inst emitter_4 of emitter_4 @[group.scala 32:46]
    inst emitter_5 of emitter_5 @[group.scala 32:46]
    inst emitter_6 of emitter_6 @[group.scala 32:46]
    inst emitter_7 of emitter_7 @[group.scala 32:46]
    inst emitter_8 of emitter_8 @[group.scala 32:46]
    inst emitter_9 of emitter_9 @[group.scala 32:46]
    inst emitter_10 of emitter_10 @[group.scala 32:46]
    inst emitter_11 of emitter_11 @[group.scala 32:46]
    inst emitter_12 of emitter_12 @[group.scala 32:46]
    inst emitter_13 of emitter_13 @[group.scala 32:46]
    inst emitter_14 of emitter_14 @[group.scala 32:46]
    inst emitter_15 of emitter_15 @[group.scala 32:46]
    node cim_fpga_state_list_0 = and(emitter.io.emitterio.cim_fpga_state, enable_array[0]) @[group.scala 33:98]
    node cim_fpga_state_list_1 = and(emitter_1.io.emitterio.cim_fpga_state, enable_array[1]) @[group.scala 33:98]
    node cim_fpga_state_list_2 = and(emitter_2.io.emitterio.cim_fpga_state, enable_array[2]) @[group.scala 33:98]
    node cim_fpga_state_list_3 = and(emitter_3.io.emitterio.cim_fpga_state, enable_array[3]) @[group.scala 33:98]
    node cim_fpga_state_list_4 = and(emitter_4.io.emitterio.cim_fpga_state, enable_array[4]) @[group.scala 33:98]
    node cim_fpga_state_list_5 = and(emitter_5.io.emitterio.cim_fpga_state, enable_array[5]) @[group.scala 33:98]
    node cim_fpga_state_list_6 = and(emitter_6.io.emitterio.cim_fpga_state, enable_array[6]) @[group.scala 33:98]
    node cim_fpga_state_list_7 = and(emitter_7.io.emitterio.cim_fpga_state, enable_array[7]) @[group.scala 33:98]
    node cim_fpga_state_list_8 = and(emitter_8.io.emitterio.cim_fpga_state, enable_array[8]) @[group.scala 33:98]
    node cim_fpga_state_list_9 = and(emitter_9.io.emitterio.cim_fpga_state, enable_array[9]) @[group.scala 33:98]
    node cim_fpga_state_list_10 = and(emitter_10.io.emitterio.cim_fpga_state, enable_array[10]) @[group.scala 33:98]
    node cim_fpga_state_list_11 = and(emitter_11.io.emitterio.cim_fpga_state, enable_array[11]) @[group.scala 33:98]
    node cim_fpga_state_list_12 = and(emitter_12.io.emitterio.cim_fpga_state, enable_array[12]) @[group.scala 33:98]
    node cim_fpga_state_list_13 = and(emitter_13.io.emitterio.cim_fpga_state, enable_array[13]) @[group.scala 33:98]
    node cim_fpga_state_list_14 = and(emitter_14.io.emitterio.cim_fpga_state, enable_array[14]) @[group.scala 33:98]
    node cim_fpga_state_list_15 = and(emitter_15.io.emitterio.cim_fpga_state, enable_array[15]) @[group.scala 33:98]
    node _cim_fpga_result_list_T = bits(enable_array[0], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_1 = mux(_cim_fpga_result_list_T, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_0 = and(emitter.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_1) @[group.scala 34:99]
    node _cim_fpga_result_list_T_2 = bits(enable_array[1], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_3 = mux(_cim_fpga_result_list_T_2, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_1 = and(emitter_1.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_3) @[group.scala 34:99]
    node _cim_fpga_result_list_T_4 = bits(enable_array[2], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_5 = mux(_cim_fpga_result_list_T_4, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_2 = and(emitter_2.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_5) @[group.scala 34:99]
    node _cim_fpga_result_list_T_6 = bits(enable_array[3], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_7 = mux(_cim_fpga_result_list_T_6, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_3 = and(emitter_3.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_7) @[group.scala 34:99]
    node _cim_fpga_result_list_T_8 = bits(enable_array[4], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_9 = mux(_cim_fpga_result_list_T_8, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_4 = and(emitter_4.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_9) @[group.scala 34:99]
    node _cim_fpga_result_list_T_10 = bits(enable_array[5], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_11 = mux(_cim_fpga_result_list_T_10, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_5 = and(emitter_5.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_11) @[group.scala 34:99]
    node _cim_fpga_result_list_T_12 = bits(enable_array[6], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_13 = mux(_cim_fpga_result_list_T_12, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_6 = and(emitter_6.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_13) @[group.scala 34:99]
    node _cim_fpga_result_list_T_14 = bits(enable_array[7], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_15 = mux(_cim_fpga_result_list_T_14, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_7 = and(emitter_7.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_15) @[group.scala 34:99]
    node _cim_fpga_result_list_T_16 = bits(enable_array[8], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_17 = mux(_cim_fpga_result_list_T_16, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_8 = and(emitter_8.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_17) @[group.scala 34:99]
    node _cim_fpga_result_list_T_18 = bits(enable_array[9], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_19 = mux(_cim_fpga_result_list_T_18, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_9 = and(emitter_9.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_19) @[group.scala 34:99]
    node _cim_fpga_result_list_T_20 = bits(enable_array[10], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_21 = mux(_cim_fpga_result_list_T_20, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_10 = and(emitter_10.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_21) @[group.scala 34:99]
    node _cim_fpga_result_list_T_22 = bits(enable_array[11], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_23 = mux(_cim_fpga_result_list_T_22, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_11 = and(emitter_11.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_23) @[group.scala 34:99]
    node _cim_fpga_result_list_T_24 = bits(enable_array[12], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_25 = mux(_cim_fpga_result_list_T_24, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_12 = and(emitter_12.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_25) @[group.scala 34:99]
    node _cim_fpga_result_list_T_26 = bits(enable_array[13], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_27 = mux(_cim_fpga_result_list_T_26, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_13 = and(emitter_13.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_27) @[group.scala 34:99]
    node _cim_fpga_result_list_T_28 = bits(enable_array[14], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_29 = mux(_cim_fpga_result_list_T_28, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_14 = and(emitter_14.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_29) @[group.scala 34:99]
    node _cim_fpga_result_list_T_30 = bits(enable_array[15], 0, 0) @[Bitwise.scala 74:15]
    node _cim_fpga_result_list_T_31 = mux(_cim_fpga_result_list_T_30, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 74:12]
    node cim_fpga_result_list_15 = and(emitter_15.io.emitterio.cim_fpga_result, _cim_fpga_result_list_T_31) @[group.scala 34:99]
    node _T = or(cim_fpga_state_list_0, cim_fpga_state_list_1) @[group.scala 35:70]
    node _T_1 = or(_T, cim_fpga_state_list_2) @[group.scala 35:70]
    node _T_2 = or(_T_1, cim_fpga_state_list_3) @[group.scala 35:70]
    node _T_3 = or(_T_2, cim_fpga_state_list_4) @[group.scala 35:70]
    node _T_4 = or(_T_3, cim_fpga_state_list_5) @[group.scala 35:70]
    node _T_5 = or(_T_4, cim_fpga_state_list_6) @[group.scala 35:70]
    node _T_6 = or(_T_5, cim_fpga_state_list_7) @[group.scala 35:70]
    node _T_7 = or(_T_6, cim_fpga_state_list_8) @[group.scala 35:70]
    node _T_8 = or(_T_7, cim_fpga_state_list_9) @[group.scala 35:70]
    node _T_9 = or(_T_8, cim_fpga_state_list_10) @[group.scala 35:70]
    node _T_10 = or(_T_9, cim_fpga_state_list_11) @[group.scala 35:70]
    node _T_11 = or(_T_10, cim_fpga_state_list_12) @[group.scala 35:70]
    node _T_12 = or(_T_11, cim_fpga_state_list_13) @[group.scala 35:70]
    node _T_13 = or(_T_12, cim_fpga_state_list_14) @[group.scala 35:70]
    node _T_14 = or(_T_13, cim_fpga_state_list_15) @[group.scala 35:70]
    transfer.io.emitterio.cim_fpga_state <= _T_14 @[group.scala 35:39]
    node _T_15 = or(cim_fpga_result_list_0, cim_fpga_result_list_1) @[group.scala 36:72]
    node _T_16 = or(_T_15, cim_fpga_result_list_2) @[group.scala 36:72]
    node _T_17 = or(_T_16, cim_fpga_result_list_3) @[group.scala 36:72]
    node _T_18 = or(_T_17, cim_fpga_result_list_4) @[group.scala 36:72]
    node _T_19 = or(_T_18, cim_fpga_result_list_5) @[group.scala 36:72]
    node _T_20 = or(_T_19, cim_fpga_result_list_6) @[group.scala 36:72]
    node _T_21 = or(_T_20, cim_fpga_result_list_7) @[group.scala 36:72]
    node _T_22 = or(_T_21, cim_fpga_result_list_8) @[group.scala 36:72]
    node _T_23 = or(_T_22, cim_fpga_result_list_9) @[group.scala 36:72]
    node _T_24 = or(_T_23, cim_fpga_result_list_10) @[group.scala 36:72]
    node _T_25 = or(_T_24, cim_fpga_result_list_11) @[group.scala 36:72]
    node _T_26 = or(_T_25, cim_fpga_result_list_12) @[group.scala 36:72]
    node _T_27 = or(_T_26, cim_fpga_result_list_13) @[group.scala 36:72]
    node _T_28 = or(_T_27, cim_fpga_result_list_14) @[group.scala 36:72]
    node _T_29 = or(_T_28, cim_fpga_result_list_15) @[group.scala 36:72]
    transfer.io.emitterio.cim_fpga_result <= _T_29 @[group.scala 36:40]
    node _enable_array_0_T = eq(counter, UInt<1>("h1")) @[group.scala 39:35]
    enable_array[0] <= _enable_array_0_T @[group.scala 39:23]
    emitter.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter.io.enable <= enable_array[0] @[group.scala 44:25]
    emitter.io.chipio.cim_fpga_result <= io.chipio[0].cim_fpga_result @[group.scala 45:25]
    emitter.io.chipio.cim_fpga_clk <= io.chipio[0].cim_fpga_clk @[group.scala 45:25]
    emitter.io.chipio.cim_fpga_state <= io.chipio[0].cim_fpga_state @[group.scala 45:25]
    io.chipio[0].fpga_cim_cmd <= emitter.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[0].fpga_cim_data <= emitter.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_1_T = eq(counter, UInt<2>("h2")) @[group.scala 39:35]
    enable_array[1] <= _enable_array_1_T @[group.scala 39:23]
    emitter_1.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_1.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_1.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_1.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_1.io.enable <= enable_array[1] @[group.scala 44:25]
    emitter_1.io.chipio.cim_fpga_result <= io.chipio[1].cim_fpga_result @[group.scala 45:25]
    emitter_1.io.chipio.cim_fpga_clk <= io.chipio[1].cim_fpga_clk @[group.scala 45:25]
    emitter_1.io.chipio.cim_fpga_state <= io.chipio[1].cim_fpga_state @[group.scala 45:25]
    io.chipio[1].fpga_cim_cmd <= emitter_1.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[1].fpga_cim_data <= emitter_1.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_2_T = eq(counter, UInt<2>("h3")) @[group.scala 39:35]
    enable_array[2] <= _enable_array_2_T @[group.scala 39:23]
    emitter_2.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_2.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_2.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_2.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_2.io.enable <= enable_array[2] @[group.scala 44:25]
    emitter_2.io.chipio.cim_fpga_result <= io.chipio[2].cim_fpga_result @[group.scala 45:25]
    emitter_2.io.chipio.cim_fpga_clk <= io.chipio[2].cim_fpga_clk @[group.scala 45:25]
    emitter_2.io.chipio.cim_fpga_state <= io.chipio[2].cim_fpga_state @[group.scala 45:25]
    io.chipio[2].fpga_cim_cmd <= emitter_2.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[2].fpga_cim_data <= emitter_2.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_3_T = eq(counter, UInt<3>("h4")) @[group.scala 39:35]
    enable_array[3] <= _enable_array_3_T @[group.scala 39:23]
    emitter_3.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_3.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_3.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_3.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_3.io.enable <= enable_array[3] @[group.scala 44:25]
    emitter_3.io.chipio.cim_fpga_result <= io.chipio[3].cim_fpga_result @[group.scala 45:25]
    emitter_3.io.chipio.cim_fpga_clk <= io.chipio[3].cim_fpga_clk @[group.scala 45:25]
    emitter_3.io.chipio.cim_fpga_state <= io.chipio[3].cim_fpga_state @[group.scala 45:25]
    io.chipio[3].fpga_cim_cmd <= emitter_3.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[3].fpga_cim_data <= emitter_3.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_4_T = eq(counter, UInt<3>("h5")) @[group.scala 39:35]
    enable_array[4] <= _enable_array_4_T @[group.scala 39:23]
    emitter_4.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_4.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_4.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_4.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_4.io.enable <= enable_array[4] @[group.scala 44:25]
    emitter_4.io.chipio.cim_fpga_result <= io.chipio[4].cim_fpga_result @[group.scala 45:25]
    emitter_4.io.chipio.cim_fpga_clk <= io.chipio[4].cim_fpga_clk @[group.scala 45:25]
    emitter_4.io.chipio.cim_fpga_state <= io.chipio[4].cim_fpga_state @[group.scala 45:25]
    io.chipio[4].fpga_cim_cmd <= emitter_4.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[4].fpga_cim_data <= emitter_4.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_5_T = eq(counter, UInt<3>("h6")) @[group.scala 39:35]
    enable_array[5] <= _enable_array_5_T @[group.scala 39:23]
    emitter_5.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_5.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_5.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_5.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_5.io.enable <= enable_array[5] @[group.scala 44:25]
    emitter_5.io.chipio.cim_fpga_result <= io.chipio[5].cim_fpga_result @[group.scala 45:25]
    emitter_5.io.chipio.cim_fpga_clk <= io.chipio[5].cim_fpga_clk @[group.scala 45:25]
    emitter_5.io.chipio.cim_fpga_state <= io.chipio[5].cim_fpga_state @[group.scala 45:25]
    io.chipio[5].fpga_cim_cmd <= emitter_5.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[5].fpga_cim_data <= emitter_5.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_6_T = eq(counter, UInt<3>("h7")) @[group.scala 39:35]
    enable_array[6] <= _enable_array_6_T @[group.scala 39:23]
    emitter_6.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_6.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_6.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_6.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_6.io.enable <= enable_array[6] @[group.scala 44:25]
    emitter_6.io.chipio.cim_fpga_result <= io.chipio[6].cim_fpga_result @[group.scala 45:25]
    emitter_6.io.chipio.cim_fpga_clk <= io.chipio[6].cim_fpga_clk @[group.scala 45:25]
    emitter_6.io.chipio.cim_fpga_state <= io.chipio[6].cim_fpga_state @[group.scala 45:25]
    io.chipio[6].fpga_cim_cmd <= emitter_6.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[6].fpga_cim_data <= emitter_6.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_7_T = eq(counter, UInt<4>("h8")) @[group.scala 39:35]
    enable_array[7] <= _enable_array_7_T @[group.scala 39:23]
    emitter_7.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_7.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_7.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_7.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_7.io.enable <= enable_array[7] @[group.scala 44:25]
    emitter_7.io.chipio.cim_fpga_result <= io.chipio[7].cim_fpga_result @[group.scala 45:25]
    emitter_7.io.chipio.cim_fpga_clk <= io.chipio[7].cim_fpga_clk @[group.scala 45:25]
    emitter_7.io.chipio.cim_fpga_state <= io.chipio[7].cim_fpga_state @[group.scala 45:25]
    io.chipio[7].fpga_cim_cmd <= emitter_7.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[7].fpga_cim_data <= emitter_7.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_8_T = eq(counter, UInt<4>("h9")) @[group.scala 39:35]
    enable_array[8] <= _enable_array_8_T @[group.scala 39:23]
    emitter_8.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_8.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_8.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_8.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_8.io.enable <= enable_array[8] @[group.scala 44:25]
    emitter_8.io.chipio.cim_fpga_result <= io.chipio[8].cim_fpga_result @[group.scala 45:25]
    emitter_8.io.chipio.cim_fpga_clk <= io.chipio[8].cim_fpga_clk @[group.scala 45:25]
    emitter_8.io.chipio.cim_fpga_state <= io.chipio[8].cim_fpga_state @[group.scala 45:25]
    io.chipio[8].fpga_cim_cmd <= emitter_8.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[8].fpga_cim_data <= emitter_8.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_9_T = eq(counter, UInt<4>("ha")) @[group.scala 39:35]
    enable_array[9] <= _enable_array_9_T @[group.scala 39:23]
    emitter_9.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_9.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_9.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_9.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_9.io.enable <= enable_array[9] @[group.scala 44:25]
    emitter_9.io.chipio.cim_fpga_result <= io.chipio[9].cim_fpga_result @[group.scala 45:25]
    emitter_9.io.chipio.cim_fpga_clk <= io.chipio[9].cim_fpga_clk @[group.scala 45:25]
    emitter_9.io.chipio.cim_fpga_state <= io.chipio[9].cim_fpga_state @[group.scala 45:25]
    io.chipio[9].fpga_cim_cmd <= emitter_9.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[9].fpga_cim_data <= emitter_9.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_10_T = eq(counter, UInt<4>("hb")) @[group.scala 39:35]
    enable_array[10] <= _enable_array_10_T @[group.scala 39:23]
    emitter_10.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_10.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_10.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_10.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_10.io.enable <= enable_array[10] @[group.scala 44:25]
    emitter_10.io.chipio.cim_fpga_result <= io.chipio[10].cim_fpga_result @[group.scala 45:25]
    emitter_10.io.chipio.cim_fpga_clk <= io.chipio[10].cim_fpga_clk @[group.scala 45:25]
    emitter_10.io.chipio.cim_fpga_state <= io.chipio[10].cim_fpga_state @[group.scala 45:25]
    io.chipio[10].fpga_cim_cmd <= emitter_10.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[10].fpga_cim_data <= emitter_10.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_11_T = eq(counter, UInt<4>("hc")) @[group.scala 39:35]
    enable_array[11] <= _enable_array_11_T @[group.scala 39:23]
    emitter_11.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_11.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_11.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_11.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_11.io.enable <= enable_array[11] @[group.scala 44:25]
    emitter_11.io.chipio.cim_fpga_result <= io.chipio[11].cim_fpga_result @[group.scala 45:25]
    emitter_11.io.chipio.cim_fpga_clk <= io.chipio[11].cim_fpga_clk @[group.scala 45:25]
    emitter_11.io.chipio.cim_fpga_state <= io.chipio[11].cim_fpga_state @[group.scala 45:25]
    io.chipio[11].fpga_cim_cmd <= emitter_11.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[11].fpga_cim_data <= emitter_11.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_12_T = eq(counter, UInt<4>("hd")) @[group.scala 39:35]
    enable_array[12] <= _enable_array_12_T @[group.scala 39:23]
    emitter_12.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_12.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_12.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_12.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_12.io.enable <= enable_array[12] @[group.scala 44:25]
    emitter_12.io.chipio.cim_fpga_result <= io.chipio[12].cim_fpga_result @[group.scala 45:25]
    emitter_12.io.chipio.cim_fpga_clk <= io.chipio[12].cim_fpga_clk @[group.scala 45:25]
    emitter_12.io.chipio.cim_fpga_state <= io.chipio[12].cim_fpga_state @[group.scala 45:25]
    io.chipio[12].fpga_cim_cmd <= emitter_12.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[12].fpga_cim_data <= emitter_12.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_13_T = eq(counter, UInt<4>("he")) @[group.scala 39:35]
    enable_array[13] <= _enable_array_13_T @[group.scala 39:23]
    emitter_13.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_13.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_13.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_13.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_13.io.enable <= enable_array[13] @[group.scala 44:25]
    emitter_13.io.chipio.cim_fpga_result <= io.chipio[13].cim_fpga_result @[group.scala 45:25]
    emitter_13.io.chipio.cim_fpga_clk <= io.chipio[13].cim_fpga_clk @[group.scala 45:25]
    emitter_13.io.chipio.cim_fpga_state <= io.chipio[13].cim_fpga_state @[group.scala 45:25]
    io.chipio[13].fpga_cim_cmd <= emitter_13.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[13].fpga_cim_data <= emitter_13.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_14_T = eq(counter, UInt<4>("hf")) @[group.scala 39:35]
    enable_array[14] <= _enable_array_14_T @[group.scala 39:23]
    emitter_14.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_14.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_14.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_14.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_14.io.enable <= enable_array[14] @[group.scala 44:25]
    emitter_14.io.chipio.cim_fpga_result <= io.chipio[14].cim_fpga_result @[group.scala 45:25]
    emitter_14.io.chipio.cim_fpga_clk <= io.chipio[14].cim_fpga_clk @[group.scala 45:25]
    emitter_14.io.chipio.cim_fpga_state <= io.chipio[14].cim_fpga_state @[group.scala 45:25]
    io.chipio[14].fpga_cim_cmd <= emitter_14.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[14].fpga_cim_data <= emitter_14.io.chipio.fpga_cim_data @[group.scala 45:25]
    node _enable_array_15_T = eq(counter, UInt<5>("h10")) @[group.scala 39:35]
    enable_array[15] <= _enable_array_15_T @[group.scala 39:23]
    emitter_15.io.systemclk <= io.systemclk @[group.scala 40:28]
    emitter_15.io.systemRstn <= io.systemRstn @[group.scala 41:29]
    emitter_15.io.emitterio.fpga_cim_cmd <= transfer.io.emitterio.fpga_cim_cmd @[group.scala 42:41]
    emitter_15.io.emitterio.fpga_cim_data <= transfer.io.emitterio.fpga_cim_data @[group.scala 43:41]
    emitter_15.io.enable <= enable_array[15] @[group.scala 44:25]
    emitter_15.io.chipio.cim_fpga_result <= io.chipio[15].cim_fpga_result @[group.scala 45:25]
    emitter_15.io.chipio.cim_fpga_clk <= io.chipio[15].cim_fpga_clk @[group.scala 45:25]
    emitter_15.io.chipio.cim_fpga_state <= io.chipio[15].cim_fpga_state @[group.scala 45:25]
    io.chipio[15].fpga_cim_cmd <= emitter_15.io.chipio.fpga_cim_cmd @[group.scala 45:25]
    io.chipio[15].fpga_cim_data <= emitter_15.io.chipio.fpga_cim_data @[group.scala 45:25]

